1. Field of the Invention
The present invention relates to a displaying apparatus. More specifically, the present invention relates to a displaying apparatus using a raster scanning type display, for example, such as a CRT display and similar devices.
2. Description of the Prior Art
Displaying apparatus capable of changing sizes of an object displayed are on a screen or a display disclosed in, for example, Japanese Patent Publication No. 45225/1980 published on Nov. 17, 1980 corresponding to U.S. Pat. No. 4,107,665. The prior art uses a VCO (Voltage Controlled Oscillator), an oscillation frequency of the VCO is changed in response to a data from a CPU and an address counter is incremented synchronously with an oscillation output. Accordingly, the higher the oscillation frequency of the VCO, the smaller the object displayed on the screen. Conversely, the longer an oscillation period of the VCO, the longer the addressing time, accordingly the size of the object is enlarged. In the prior art, thus, the size of object displayed is changed by varying the oscillation frequency of the VCO. Such technique may be applied, for example, advantageously in a TV game equipment.
However, in the prior art described above, since an analog circuit element such as the VCO is used, an exacting frequency control is required. Moreover, since a charge/discharge circuit having a capacitor is included, there was a difficulty not only of adjusting a value of the capacitor, etc. but also in fabricating such capacitive circuit in a large scale integrated circuit (LSI). Furthermore, since a changing rate of the frequency of the VCO is exactly the ratio of image enlargement and reduction and the range of the frequency rate change is limited by the capacitor circuit, the enlargement and reduction ratio can not be increased much.
An alternative proposal using the above cited large scale integrated circuit, it might be possible to use a digital circuit including a reference oscillator and a programmable frequency divider in place of the VCO for generating a clock signal for an address counter. That is, a count input having various frequencies as in the prior art described above is obtainable by dividing an output of the reference oscillator in accordance with a division ratio from the CPU.
However, according to calculations made by the inventor of the present invention, a frequency of the reference oscillator of more than 3 GHz is required for obtaining a performance similar to the prior art by the configuration described above, but such an oscillator is not readily obtainable in practice. Further, a response speed of the programmable frequency divider must be in the range of about 325 pico-seconds, but such a high response speed in a programmable frequency divider is, practically, not available. Accordingly, the digital circuit cannot be implemented merely by using the concept taught by the prior art cited above.